This invention relates generally to the chemical-mechanical planarization (CMP) of tungsten-containing substrates on semiconductor wafers and slurry compositions therefor. This invention is especially useful for tungsten CMP where low dishing/plug recess and low array erosion on planarized substrates is desired and/or required.
Chemical mechanical planarization (chemical mechanical polishing, CMP) for planarization of semiconductor substrates is now widely known to those skilled in the art and has been described in numerous patents and open literature publications. An introductory reference on CMP is as follows: “Chemical-Mechanical Polish” by G. B. Shinn et al., Chapter 15, pages 415-460, in Handbook of Semiconductor Manufacturing Technology, editors: Y. Nishi and R. Doering, Marcel Dekker, New York City (2000).
In a typical CMP process, a substrate (e.g., a wafer) is placed in contact with a rotating polishing pad attached to a platen. A CMP slurry, typically an abrasive and chemically reactive mixture, is supplied to the pad during CMP processing of the substrate. During the CMP process, the pad (fixed to the platen) and substrate are rotated while a wafer carrier system or polishing head applies pressure (downward force) against the substrate. The slurry accomplishes the planarization (polishing) process by chemically and mechanically interacting with the substrate film being planarized due to the effect of the rotational movement of the pad parallel to the substrate. Polishing is continued in this manner until the desired film on the substrate is removed with the usual objective being to effectively planarize the substrate. Typically metal CMP slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium.
There are a large number of materials used in the manufacture of integrated circuits such as a semiconductor wafer. The materials generally fall into three categories—dielectric material, adhesion and/or barrier layers, and conductive layers. The use of the various substrates, e.g., dielectric material such as TEOS, PETEOS, and low-k dielectric materials; barrier/adhesion layers such as tantalum, titanium, tantalum nitride, and titanium nitride; and conductive layers such as copper, aluminum, tungsten, and noble metals are known in the industry.
Integrated circuits are interconnected through the use of well-known multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and typically third and subsequent levels of metallization. Interlevel dielectric materials such as silicon dioxide and sometimes low-k materials are used to electrically isolate the different levels of metallization in a silicon substrate or well. The electrical connections between different interconnection levels are made through the use of metallized vias and in particular tungsten vias. U.S. Pat. No. 4,789,648 describes a method for preparing multiple metallized layers and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts are generally filled with tungsten and generally employ an adhesion layer such as titanium nitride (TiN) and/or titanium to adhere a metal layer such as a tungsten metal layer to the dielectric material.
In one semiconductor manufacturing process, metallized vias or contacts are formed by a blanket tungsten deposition followed by a CMP step. In a typical process, via holes are etched through the interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a thin adhesion layer such as titanium nitride and/or titanium is generally formed over the ILD and is directed into the etched via hole. Then, a tungsten film is blanket deposited over the adhesion layer and into the via. The deposition is continued until the via hole is filled with tungsten. Finally, the excess tungsten is removed by chemical mechanical polishing (CMP) to form metal vias.
The ratio of the removal rate of a metal (e.g., tungsten) to the removal rate of a dielectric base is called the “selectivity” for removal of the metal in relation to removal of the dielectric during CMP processing of substrates comprised of metal and dielectric material. When CMP slurries with high selectivity for removal of metal in relation to dielectric are used, the metal layers are easily over-polished creating a depression or “dishing” effect in the metalized areas. This feature distortion is unacceptable due to lithographic and other constraints in semiconductor manufacturing.
Another feature distortion that is unsuitable for semiconductor manufacturing is called “erosion.” Erosion is the topography difference between a field of dielectric and a dense array of metal vias or trenches. In CMP, the materials in the dense array may be removed or eroded at a faster rate than the surrounding field of dielectric. This causes a topography difference between the field of dielectric and the dense metal (e.g., copper or tungsten) array.
As industry standards trend toward smaller device features, there is an ever-developing need for CMP slurries that deliver superior planarization of the nanostructures of IC chips. Specifically, for 45 nm technology nodes and smaller feature sizes, slurry products must deliver low removal rate selectivity between metal and dielectric, thereby lowering erosion while maintaining sufficient removal rate and low defect levels. Furthermore, in the competitive market of CMP consumables, low cost of ownership (CoO), specifically through concentration of CMP slurry, is quickly becoming an industry standard.
A typically used CMP slurry has two actions, a chemical component and a mechanical component. An important consideration in slurry selection is “passive etch rate.” The passive etch rate is the rate at which a metal (e.g., copper) is dissolved by the chemical component alone and should be significantly lower than the removal rate when both the chemical component and the mechanical component are involved. A large passive etch rate leads to dishing of the metallic trenches and vias, and thus, preferably, the passive etch rate is less than 10 nanometers per minute.
These are three general types of layers that can be polished. The first layer is interlayer dielectrics (ILD), such as silicon oxide and silicon nitride. The second layer is metal layers such as tungsten, copper, aluminum, etc., which are used to connect the active devices. This application addresses polishing the metal layer, particularly tungsten. The third type of layer is an adhesion/barrier layer such as titanium nitride.
In the case of CMP of metals, the chemical action is generally considered to take one of two forms. In the first mechanism, the chemicals in the solution react with the metal layer to continuously form an oxide layer on the surface of the metal. This generally requires the addition of an oxidizer to the solution such as hydrogen peroxide, ferric nitrate, etc. Then the mechanical abrasive action of the particles continuously and simultaneously removes this oxide layer which is formed on the metal layer. A judicious balance of these two processes obtains optimum results in terms of removal rate and polished surface quality.
In the second mechanism, no protective oxide layer is formed. Instead, the constituents in the solution chemically attack and dissolve the metal, while the mechanical action is largely one of mechanically enhancing the dissolution rate by such processes as continuously exposing more surface area to chemical attack, raising the local temperature (which increases the dissolution rate) by the friction between the particles and the metal and enhancing the diffusion of reactants and products to and away from the surface by mixing and by reducing the thickness of the boundary layer.
The slurry composition is an important factor in the CMP step. Depending on the choice of the oxidizing agent, the abrasive, and other useful additives, the polishing slurry can be tailored to provide effective polishing of metal layers at desired polishing rates while minimizing surface imperfections, defects, corrosion, and erosion of oxide in areas with tungsten vias. Furthermore, the polishing slurry may be used to provide controlled polishing selectivity to other thin-film materials used in current integrated circuit technology such as titanium, titanium nitride and the like.
There is a significant need for tungsten CMP process(es) and slurry(s) that afford low dishing and plug recess effects especially in view of the fact that the semiconductor industry continues to move towards smaller and smaller feature sizes. The present invention provides a solution to this significant need.